The present invention relates to micro-miniaturized semiconductor devices comprising CMOS transistors on silicon-germanium. The present invention is particularly applicable in fabricating CMOS transistors with balanced drive currents.
The relentless pursuit of miniaturized semiconductor devices continues to challenge the limitations of conventional semiconductor materials and fabrication techniques. Conventional semiconductor devices typically comprise a plurality of active devices in or on a common semiconductor substrate, e.g., CMOS devices comprising at least a pair of PMOS and NMOS transistors in spaced adjacency. Current technology utilizes crystalline semiconductor wafers as substrates, such as a lightly p-doped epitaxial (xe2x80x9cepixe2x80x9d) layer of silicon (Si) grown on a heavily-doped, crystalline Si Substrate. The low resistance of the heavily-doped substrate is necessary for minimizing susceptibility to latch-up, whereas the light doping of the epi layer permits independent tailoring of the doping profiles of both the p-type and n-type wells formed therein as part of the fabrication sequence, thereby resulting in optimal PMOS and NMOS transistor performance.
The use of the very thin epi layers, i.e., several xcexcm thick, is made possible by utilizing shallow trench isolation (xe2x80x9cSTIxe2x80x9d), which advantageously minimizes up-diffusion of p-type dopant(s) from the more heavily-doped substrate into the lightly-doped epi layer. In addition, STI allows for closer spacing of adjacent active areas by avoiding the xe2x80x9cbird""s beakxe2x80x9d formed at the edge of each LOCOS isolation structure. STI also provides better isolation by creating a more abrupt structure, reduces the vertical step from active area to isolation to improve gate lithography control, eliminates the high temperature field oxidation step that can cause problems with large diameter, i.e., 8 inch, wafers, and is scalable to future logic technology generations.
Substrates based on xe2x80x9cstrained siliconxe2x80x9d have attracted interest as a semiconductor material which provides increased speeds of electron and hole flow therethrough, thereby permitting fabrication of semiconductor devices with higher operating speeds, enhanced performance characteristics, and lower power consumption. A very thin, tensilely strained, crystalline silicon (Si) layer is grown on a relaxed, graded composition of silicon-germanium (SiGe) buffer layer several microns thick, which SiGe buffer layer in turn is formed on a suitable crystalline substrate, e.g., a Si wafer or a silicon-on-insulator (SOI) wafer. The SiGe buffer layer typically contains 12 to 25 at. % Ge. Strained Si technology is based upon the tendency of the Si atoms, when deposited on the SiGe buffer layer, to align with the greater lattice constant (spacing) of Si and Ge atoms therein (relative to pure Si). As a consequence of the Si atoms being deposited on a substrate (SiGe) comprised of atoms which are spaced further apart, they xe2x80x9cstretchxe2x80x9d to align with the underlying Si and Ge atoms, thereby xe2x80x9cstretchingxe2x80x9d or tensilely straining the deposited Si layer. Electrons and holes in such strained Si layers have greater mobility than in conventional, relaxed Si layers with smaller inter-atom spacings, i.e., there is less resistance to electron and/or hole flow. For example, electron flow in strained Si may be up to about 70% faster compared to electron flow in conventional Si. Transistors and IC devices formed with such strained Si layers can exhibit operating speeds up to about 35% faster than those of equivalent devices formed with conventional Si, without necessity for reduction in transistor size.
The mobility of electrons is faster than the mobility of holes in conventional bulk silicon substrates. Accordingly, in conventional CMOS transistors, the drive current of the PMOS transistor is less than the drive current of the NMOS transistor creating an imbalance. This imbalance is exacerbated in CMOS transistors fabricated on or within a tensilely stressed active device area formed in a strained lattice semiconductor substrate, e.g., strained Si on SiGe, because the increase in electron mobility is greater than the increase in hole mobility.
Accordingly, there exists a need for methodology enabling the fabrication of semiconductor devices comprising narrow width CMOS transistors with balanced drive currents.
An advantage of the present invention is a method of fabricating a semiconductor device comprising CMOS transistors with balanced drive currents.
Another advantage of the present invention is a semiconductor device comprising CMOS transistors with balanced drive currents.
Additional advantages andid other aspects and features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are obtained in part by a method of manufacturing a semiconductor device comprising a PMOS transistor and an NMOS transistor, the method comprising; forming a substrate comprising a layer of silicon (Si) having a strained lattice on a layer of silicon-germanium (SiGe); forming isolation regions defining a PMOS region and an NMOS region; forming a thermal oxide layer on the strained Si layer in the PMOS and NMOS regions; selectively removing the thermal oxide layer and strained Si layer from the SiGe layer in the PMOS region; depositing a layer of dielectric material on the layer of SiGe in the PMOS region; and forming transistors in the PMOS and NMOS regions, wherein: a portion of the thermal oxide layer serves as the gate dielectric layer of the NMOS transistor, and a portion of the deposited layer of dielectric material serves as the gate dielectric layer of the PMOS transistor.
Another advantage of the present invention is a semiconductor device comprising: a substrate comprising a layer of silicon-germanium (SiGe); a PMOS transistor comprising: a gate dielectric layer of material having a high dielectric constant (k) of 10 or more deposited on the layer of SiGe; a gate electrode on the gate dielectric layer, and an NMOS transistor comprising: a layer of strained silicon (Si) on the layer of SiGe; a thermally formed gate oxide layer on the layer of strained Si; and a gate electrode on the thermally formed gate oxide layer.
Embodiments of the present invention comprise depositing, as by chemical vapor deposition (CVD), a dielectric material having a high dielectric constant (k) of 10 or higher on the SiGe layer in the PMOS region, as at a thickness of 10 xc3x85 to 50 xc3x85. Embodiments of the present invention comprise forming the thermal oxide layer at a thickness of 10 xc3x85 to 20 xc3x85, which is less than the thickness of the layer of high dielectric constant (k) material which serves as the gate dielectric layer for the PMOS transistor.
Additional advantages and aspects of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein embodiments of the present invention are shown and described, simply by way of illustration of the best mode contemplated for practicing the present invention. As will be described, the present invention is capable of other and different embodiments, and its several details are susceptible of modification in various obvious respects, all without departing from the spirit of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as limitative.